1. Technical Field
Embodiments described herein relate to integrated circuits, and more particularly, to techniques for tuning circuit paths within a multi-port memory.
2. Description of the Related Art
Processors, memories, and other types of integrated circuits, typically include a number of logic circuits composed of interconnected transistors fabricated on a semiconductor substrate. Such logic circuits may be constructed according to a number of different circuit design styles. For example, combinatorial logic may be implemented via a collection of un-clocked static complementary metal-oxide semiconductor (CMOS) gates situated between clocked state elements such as flip-flops or latches. Alternatively, depending on design requirements, some combinatorial logic functions may be implemented using clocked dynamic logic, such as domino logic gates.
Wires formed from metallization layers available on a semiconductor manufacturing process may be used to connect the various clocked state elements and logic gates. Manufacturing variation from chip to chip as well as differences in physical routing of the wires may result in different propagation times between logic gates.
During operation, voltage levels of various on-chip power supplies may vary. Such variation may be the result of voltage drops across parasitic circuit elements during increased levels of activity of logic switching. In addition, a temperature of an integrated circuit may fluctuate in response to the ambient temperature as well as the level of activity of logic switching. Fluctuation of voltage levels and temperature may also impact the propagation delays between logic gates.
A system-on-a-chip (SoC) may include one or more processors along with various other functional blocks implemented within a single integrated circuit. SoCs may also include one or more volatile memories such as static random access memory (SRAM) and/or register files. In some instances, a volatile memory may be capable of receiving data values for storage from two or more sources in a single system clock cycle. Such memories may be referred to as multi-port memories. Furthermore, some such multi-port memories may be capable of writing two received data values in a single system clock cycle, referred to as double pumped writes.
A double pumped, multi-port memory may write a first data value during a first half of a system clock cycle and write a second data value during a second half of the same cycle. A double pumped memory may, therefore, be more sensitive to variations in manufacturing as well as voltage and temperature effects than a single port memory. If the write circuitry of the memory is sensitive to such effects, then processing variations may cause low yields during a production test flow and/or may limit voltage and temperature operating ranges of the SoC.